Text from the interactive explanation

Reconfigurable In-Memory Computing Using Standard 6T SRAM for BCAM, TCAM, Similarity Indexing, and Logic-in-Memory Operations

Eman Hassan, K M Shadid Hassan, Shaymaa Elshahaby, Baker Mohammad

An interactive guide to a 2025 preprint · tested in 22 nm chip simulations

Every chip already carries SRAM, the fast memory that answers “what is stored at address N?”. This research shows the same standard cells answering a different question in a single clock tick: “where is something like this?”

bitline charge

wordline pulse (the question)

mismatch draining charge

best match

Each column is one stored 16-bit word: a 4×4 picture on top, the same bits as 16 pairs of memory cells below, and an amber bitline “tube” beside them. The search key on the left is sent along the wordlines to every column at once.

Draw your search key

Tap pixels (or drag across them). Each pixel is one search bit.

The long walk to memory

Ordinary memory is a huge set of numbered boxes. A processor asks “what is in box 41?” and the answer travels back over a bus. To find a pattern, it has to fetch boxes one after another and compare each one itself. All that shuttling between memory and processor costs time and energy. Engineers call it the memory wall , and the paper notes it weighs heavily on AI workloads such as deep neural networks and hyperdimensional computing, especially when they run inference.

A content-addressable memory (CAM) turns the question around. You hand it the pattern, and every stored word compares itself with it at the same moment. The answer, which words match, comes back in one or two clock cycles.

Illustrative counting model: one fetch-and-compare per trip for the processor, one compare-everything pulse for the CAM.

CAMs exist. Why isn’t every memory one?

Because comparing costs hardware. A standard SRAM cell uses 6 transistors. A conventional binary CAM cell adds a 4-transistor comparator (10T), and a ternary CAM cell, which can also store “don’t care”, needs 16. The paper cites CAM arrays 2–5 times larger than SRAM of the same capacity, with the power and chip area that come with it.

Could the plain 6-transistor cells that are already in every chip do the comparing themselves?

Inside one memory cell

An SRAM cell is a tiny seesaw. Two inverters (each turns a 1 into a 0 and back) feed each other in a loop, so the cell settles with one side high and the other low, and stays that way. One side, Q , holds the bit; the other, Q (“Q-bar”), holds its opposite.

Two more transistors act as doors . A horizontal wire, the wordline (WL) , opens both at once. Behind each door runs a vertical wire, a bitline : BL on the Q side, BLB on the Q side. Before a read, both bitlines are charged up to the supply voltage (“precharged”). Then the wordline opens the doors.

Predict first: with the cell storing 1, which bitline will lose its charge?

The side that holds 0 drains its bitline. That single rule is everything the rest of this design builds on.

What if you stack two cells, one holding the bit and one holding its opposite, and open only one of them?

Two cells make a comparator

The reconfigurable SRAM (R-SRAM) in this paper stores every bit twice, in the same column: the top cell holds the bit (Q) and the cell just below holds its opposite (Q). The question arrives on the wordlines. A search bit of 1 opens the top cell’s doors (WL); a search bit of 0 opens the bottom cell’s doors (WLB).

Try all four combinations of stored bit and search bit. Predict what BL does before you press Search; the table fills in as you go.

BL drains exactly when the two bits differ. That is a mismatch detector built from two plain memory cells, with no extra comparison gates: the authors write that the dual-cell approach “eliminates the need for glue logic”. The honest cost is two cells per bit, 12 transistors. But they are the foundry’s standard, densely packed SRAM cells: 0.246 µm² per bit in the authors’ 22 nm layout.

One pair compares one bit. What happens when a whole column of pairs shares the same bitline?

A column is a word, the wordlines are the question

Stack pairs in a column and you have a word sharing one BL. Put columns side by side and drive all the wordlines at once: every column compares itself with the search word at the same time. One mismatching pair is enough to drain a column’s BL; only a full match leaves it high. A sense amplifier (SA) at the foot of each column compares BL with BLB and reports match or mismatch.

Here is the paper’s own small example (its Fig. 3b): four search bits, three stored words. Click any bit, on the left (the question) or inside a word (the data).

Tube drops are exaggerated so you can see them. Pair legend: the top square is the Q cell, the bottom one the Q cell; a lit square stores 1. The cyan line shows which door each search bit opens.

At full scale the authors simulated a 32 × 64 array: 64 columns, each holding a 16-bit word in 32 cells, all compared in one cycle. Only the periphery changes: a CAM wordline driver, plus a tri-state “head switch” that lets it take over the wordlines from the normal address decoder (their Fig. 2). The cell array itself is untouched.

In the authors’ post-layout simulation of this small example (Fig. 4), BL1 of the matching column stays near the precharge level while BL2 (one mismatch) and BL3 (two mismatches) sag further; the paper reports drops of about 20–25 mV per mismatch here. Writing is quick too: the whole CAM array is written in two cycles (first all the 0s, then all the 1s) instead of one step per bit. The price: reading a stored CAM word back out takes as many cycles as it has bits, which the authors accept because CAMs are mostly searched, not read.

A mismatch drains the bitline. Do two mismatches drain it more than one?

How different? Counting with charge

Yes. Each mismatching pair opens one more leak, so the BL voltage falls step by step with the number of differing bits, while BLB, drained by the matching pairs, rises in mirror image. The leftover voltage is an analog count of differing bits: the Hamming distance .

Reading that count cheaply takes two steps. The sense amplifier asks a yes/no question: is BL above BLB? Above means 0–7 mismatches (“high similarity”); below means 8–15. Then a 3-bit analog-to-digital converter (ADC) reads a code 0–7 inside that half (the paper’s Table I). So a 3-bit converter does a job that would otherwise need a 4-bit one. The authors also made BL’s capacitance deliberately smaller than BLB’s, so that even a few mismatches move BL clearly. They describe this similarity index as a first for CAM designs.

Predict: at how many differing bits does BL fall below BLB?

Values read from Fig. 9b (post-layout simulation of a 16-bit word), approximate. Amber: BL. Blue-grey: BLB.

Try it somewhere new: nearest-match search

Every column produces its own voltage in the same cycle, so the whole memory can be ranked at once: the fullest bitline belongs to the most similar word. Pick a target word, add noise, and watch the array rank its words by charge. The number under each column is how many bits differ.

The Hamming distance between two strings of bits is simply the number of positions where they differ: 1011 and 1001 are at distance 1. Hyperdimensional computing (HDC) is a style of AI that represents things such as letters, sounds or sensor readings as very long binary patterns and recognises a new input by finding the stored pattern with the smallest Hamming distance. That is exactly what the similarity index computes for every stored word in parallel. The authors list Hamming-distance operations tailored to tasks like HDC as future work.

What if some stored bits should not count at all?

“Don’t care” bits

A ternary CAM (TCAM) can store a third value, X , meaning “don’t care”: that bit matches both 0 and 1. In the R-SRAM, X is just another way of filling the cell pair. Write 1 into both cells (“11”), and neither opened cell ever pulls BL down, whatever the search bit. The encodings, top cell first: 10 stores 1, 01 stores 0, 11 stores X.

TCAMs are workhorses inside internet routers, which match every packet’s address against a table of rules with wildcards; the paper names IP router tables among CAM’s main uses. The toy table here uses 8-bit addresses (real tables use much longer addresses and many more rules). Flip address bits on the left, or tap a rule’s bits to cycle 0 → 1 → X.

In this design X costs nothing extra: TCAM uses the same 12 transistors per bit as binary CAM, and the authors report fewer write cycles than the earlier configurable SRAM-CAM they compare with.

lit cell stores 1

X pair (11): never drains BL

mismatch

Search reads down the columns. Could the same array also compute across the rows?

Compute where the data lives

Change the point of view: now each row is an operand, a word stored across the columns. Switch on the wordlines of two rows at once. In every column, BL stays high only if both selected cells hold 1, because any 0 pulls it down: BL computes AND . BLB stays high only if both hold 0: BLB computes NOR . A little logic outside the array combines the two into XNOR (“are the bits equal?”). Switch on a single row and BLB delivers its inverse, NOT .

All columns compute in parallel, and the operands never leave the memory. That is the core promise of in-memory computing.

Switch row wordlines on or off; tap any bit to change it.

With so many cells opened at once, could a search disturb the very data it is reading?

Don’t wake the cell

Opening a cell’s doors connects its delicate latch to a charged bitline. During a search many cells on the same bitline open together, and if the wordline voltage is too high the bitline can push the seesaw over. The wordline voltage is a trade-off (the paper’s Fig. 9a): higher means more read current , so a faster read, but a smaller static noise margin (SNM) , the amount of electrical noise the latch tolerates before it flips.

SNM has a neat picture. Plot the two inverters’ response curves on top of each other and you get a “butterfly”; the SNM is the side of the largest square that fits inside one wing (Fig. 7).

Your mission: push the wordline voltage up for speed. Where does the data break?

Illustrative curves: a simple inverter model tuned so the square’s side equals the SNM read from Fig. 9a at each voltage.

The authors chose stability. In their simulations the stored data survives with the wordline at 0.5 V and flips when it is raised to 0.6–0.8 V, so they run search and logic at a 0.5 V wordline , where the SNM is 274 mV, against 142 mV at 0.8 V. The CAM wordline driver also switches its own supply: the standard 0.8 V for writes and a lower 0.6 V for searches, so that searching does not overwrite the cells. Storing each bit and its complement in separate cells also helps keep the data intact during a search, the authors note.

That was one ideal cell. Real chips are never perfectly identical. Does the search survive manufacturing variation?

A thousand imperfect chips

No two manufactured transistors are exactly alike: their threshold voltages and the mobility of their charge carriers vary at random. The authors ran Monte Carlo simulations , virtually building the circuit again and again with random variations drawn from the foundry’s statistical models, and recorded the bitline voltage each time. For every mismatch count the results form a bell curve (their Fig. 12).

Below, each falling dot is one virtual chip, drawn from bell curves read off Fig. 12. Watch how the spread grows with the number of mismatches k: tight at 0, wide at 16.

Re-sampled from Gaussian curves read off Fig. 12 (centres from Fig. 9b, spreads from the peak heights); illustrative, not the authors’ raw simulation runs.

Wider curves overlap more, and the authors point out that a larger spread means more sensitivity to read errors. Here the low counts (0, 1, 2) stay sharply separated, while neighbouring curves at the high end (15, 16) overlap. To keep margins healthy they point to transistor upsizing, differential sensing and assist circuits.

So what does all of this buy, in numbers?

What the simulations showed

All from the authors’ post-layout simulations (with Monte Carlo analysis) of a 32 × 64 array in a 22 nm FDSOI foundry process.

A femtojoule (fJ) is a millionth of a billionth of a joule. Simple arithmetic, ours rather than the paper’s: 16 bits × 64 words × 0.441 fJ ≈ 0.45 pJ to compare one key with the entire array.

The authors report about 25% lower energy per search than the best previous work in their table, and 1000 MHz against 370 MHz for [17], an earlier configurable SRAM-CAM also built on 6T cells. The rows use different process nodes and supply voltages, which also shape energy, and the authors credit part of the gain to the 22 nm process and the lower voltages it allows.

One array, many jobs. Time to see them side by side.

One array, five jobs

Same physical cells, same bitlines. What changes is who drives the wordlines (the normal address decoder, or the search driver, selected by the tri-state switch) and what the bitlines mean. Turn the dial.

That is what this design brings closer: memory that every chip already contains, built from standard foundry cells rather than emerging, still commercially immature devices such as ReRAM, doing similarity search and logic without shuttling data to a processor. AI inference, edge devices, router tables, bioinformatics and image processing are among the uses the paper names.

It is a simulation study and a first step. The authors’ next steps: Hamming-distance operations tailored to tasks such as hyperdimensional computing, efficient ADC integration, and more work on robustness and fault tolerance for writes and searches.

Back to the search ↑

Source & credits

Eman Hassan, K M Shadid Hassan, Shaymaa Elshahaby, Baker Mohammad. “Reconfigurable In-Memory Computing Using Standard 6T SRAM for BCAM, TCAM, Similarity Indexing, and Logic-in-Memory Operations.” TechRxiv preprint, version 1, posted 22 April 2025. doi.org/10.36227/techrxiv.174535561.12992273/v1 (TechRxiv page).

Status: a preprint that has not been peer reviewed. All results described here come from the authors’ post-layout and Monte Carlo simulations in a 22 nm FDSOI process.

License: the paper is published under CC BY 4.0.

Figures: Figs. 3a, 4, 8 and 12 are from Hassan et al. 2025, CC BY 4.0; resized and cropped from the original PDF.

Data: curve values were read from Figs. 9 and 12 by eye and are approximate; table values are as reported in Tables II and III.

Illustrations: all animations are illustrative renderings of the paper’s mechanism, slowed about a billion times (10⁹×). The 4×4 glyph words, the processor-vs-CAM race, the toy router table, the logic rows, the butterfly curve model and the Monte Carlo re-sampling are illustrative.

Fonts: Fraunces, Space Grotesk and JetBrains Mono, under the SIL Open Font License.